Relentless efforts at miniaturization are bringing traditional CMOS devices to the limit where the device characteristics are governed by quantum phenomena; in such regimes, perfect control is impossible to achieve. This has engendered a need for finding alternative new materials to fabricate devices that will possess at least the same or even better performance than existing CMOS devices but with greater control.
The miniaturization of CMOS devices has hitherto been governed by a trend—often called Moore's law—in which electronic components shrink in size by half every 30 months. The International Technology Roadmap for Semiconductors (ITRS) has established a projected growth curve according to this model. The demands for speed, high integration level, high performance and low production costs attendant on such a rate of progress are very stringent. Consequently, the problems associated with the physical and electrical characteristics of traditional materials used for making devices have escalated. Hence there is a need to search for alternative solutions to the problems that will impede the progress of silicon technology in the immediate future. This means that devising innovative materials and processes is critical to sustaining the projected rate of growth.
The ITRS emphasizes the high speed transmission needs of the chip as the driver for future interconnect development for both high performance microprocessors (MPs) and dynamic random access memory (DRAM). State of the art microprocessors are mostly made of a two dimensional layer of silicon based components, connected to one another with up to nine layers of metal interconnects (see, e.g., Graham, A. P.; Duesberg, G. S.; Seidel, R.; Liebau, M.; Unger, E.; Kreupl, F.; Honlein, W., Diamond and Related Materials, (2004), 13, (4-8), 1296). Therefore, interconnect technology plays a vital role in semiconductor technology and merits special emphasis.
The choice of new materials is however limited by factors such as compatibility with existing production methods, reproducibility of manufacture and cost. In general, the challenges of interconnect technology arise from both material requirements and difficulties in processing (Jun, L.; Qi, Y.; Cassell, A.; Hou Tee, N.; Stevens, R.; Jie, H.; Meyyappan, M. Applied Physics Letters, 82, (15), 2491, (2003)). Some problems that existing materials used in semiconductor technology have faced are as follows.
Currently, device performance is degraded due to high leakage current through gate oxide (which is very thin). This in turn increases the leakage current in the off state, and hence increases power consumption, which in turn can reduce the lifetime of a battery.
Cu interconnects perform poorly. Due to its low resistivity, copper is used for making interconnects that connect various components to one another, as well as to external devices and circuits. Due to the dramatic reduction in the size of the components, interconnects based on copper material are now showing poor performance in terms of current carrying capacity and lifetime of the wires, and are also becoming more difficult and costly to fabricate. In particular, a phenomenon known as electromigration threatens the reliability of nanometer-size copper interconnects at high current densities (106 A/cm2 and above). This is a matter of concern since by the year 2013 it will be a requirement for interconnects to handle such current densities (see, e.g., Jun, L., et al., Applied Physics Letters, 82, (15), 2491, (2003); ITRS, Semiconductor Roadmap, (2003)). Electromigration causes internal and external cavities that lead to wire failure. Moreover, due to interface roughness and small grain size, the electrical resistivity of metals increases with a decrease in dimensions (Jun, L., et al., Applied Physics Letters, 82, (15), 2491, (2003)). Such size induced effects of metal interconnects are difficult to avoid. All of these factors in turn reduce the lifetime of a processor. No solution currently exists for interconnects that will efficiently connect the devices in a circuit with those outside of the circuit, in time to meet the projected demand for current density over the next several years.
Demand is increasing for high aspect ratio structures. Today the aspect ratio of contact holes for interconnects in DRAM stacked capacitors has reached 12:1 and is expected to increase to 23:1 by the year 2016 (ITRS, Semiconductor Roadmap, (2003)). Creating such high aspect ratio contacts with straight walls poses substantial technological challenges, not least because void-free filling with metals (also known as vias) of such high aspect ratio features is extremely difficult.
Modern microprocessors generate inordinate amounts of heat. Heat dissipation has been increasing steadily as the transistor count and clock frequency of computer processors has increased (see, e.g., Thompson, S., et al., in A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm2 SRAM cell, San Francisco, Calif., United States, Institute of Electrical and Electronics Engineers Inc., 2002 at p 61). In particular, for example, copper interconnects of the sizes required for current and future devices generate so much heat that their electrical resistance is increased, thereby leading to a decreased capacity to carry current. Although device and system manufacturers have so far managed to channel that heat away, the task is becoming more difficult and challenging as microprocessors get faster and smaller. A practical solution for cooling of such systems that will not eventually exceed the power budget for processors has yet to be found.
In short, for all these reasons, it has become necessary to search for alternative materials and processing technology.
Carbon nanostructures, including carbon nanotubes (CNT's) and carbon nanofibers (CNF's), are considered to be some of the most promising candidates for future developments in nano-electronics, nano-electromechanical systems (NEMS), sensors, contact electrodes, nanophotonics, and nano-biotechnology. This is due principally to their one dimensional nature and their unique electrical, optical and mechanical properties. In contrast to the fullerenes, such as C60 and C70, whose principal chemistry is based on attaching specific functionalities to produce specific properties, CNTs offer almost limitless variation through design and manufacture of tubes of different diameters, pitches, and lengths. Furthermore, whereas the fullerenes offer the possibility of making a variety of discrete molecules with specific chemical properties, carbon nanotubes and carbon nanofibers provide the possibility to make molecular-scale components that have excellent electrical and thermal conductivity, and strength. (See, e.g., Nanoelectronics and Information Technology, R. Waser (Ed.), Wiley-VCH, 2003, at chapter 19.)
Carbon nanotubes and carbon nanofibers have been considered for both active devices and as interconnect technology at least because of their electrical and thermal properties and their strength. For example, the high electron mobility of carbon nanotubes (79,000 cm2Ns) surpasses that of state-of-the-art MOSFET devices (see, e.g., Durkop, T., et al., Nano Letters, 4(1), 35, (2004)). Furthermore, the extremely high current carrying capacity of carbon nanotubes (1010 A/cm2) (see, e.g., Wei, B. Q., et al., Appl. Phys. Lett., 79(8), 1172, (2001)), when compared with copper interconnects (˜106 A/cm2), means that carbon nanostructures potentially possess the solution to the severe problems for interconnects projected in ITRS. Additionally, copper burns out at around 106 A/cm2 while nanotubes and nanofibers can carry up to 109 A/cm2. Bundles of densely packed nanostructures can also have substantially lower resistance than copper.
Furthermore, the anisotropic thermal conductivity of nanotubes/nanofibers (6,000 W/Km) (see, e.g., Hoenlien, W., et al., IEEE Trans. Compon. and Packaging Tech., 27(4), 629, (2004)) is also exceptionally promising for solving the growing problems of heat dissipation in semiconductor devices.
The added value for a CNT/CNF via or interconnect is scalability to nanometer dimensions with a large aspect ratio. Kreupl, et al. made a comparative analysis on the resistance between CNT's and gold wires of the same dimension, and by taking size effects into account they showed that CNF's can readily compete with ordinary metallization schemes and can offer the possibility of achieving orders of magnitude lower resistance (see, e.g., Kreupl, F.; Graham, A. P.; Duesberg, G. S.; Steinhogl, W.; Liebau, A.; Unger, E.; Honlein, W., Microelectronic Engineering, (2002), 64, (1-4), 399). Recent theoretical work performed by Naeemi et al. on CNT as interconnects revealed that performance enhancement at the 45 nm node (projected in the year 2010) is negligible compared to today's copper interconnects, but at the 22 nm node (projected in the year 2016) nanotube interconnects will be up to 80% faster than copper wires. In that case, bundles of CNTs are more preferable than single CNTs due to low density of states present in the quantum wires, which induces a large kinetic inductance per unit length, which then causes slow wave propagation. Hence CNF could perhaps be better interconnect materials, since they presumably possess a higher density of states than CNT due to their structural configuration. In terms of stability during current flow, Wei et al. observed no degradation of MWCNTs after a period of 350 hours at current densities exceeding 109 A/cm2 (Wei, B. Q.; Vajtai, R.; Ajayan, P. M., Applied Physics Letters, (2001), 79, (8), 1172).
In general, it is highly desirable to fabricate electronic devices that are compatible with existing complementary metal oxide semiconductor (CMOS) fabrication techniques. A prerequisite for exploring CNTs in an industrial process is to be able to control mass production of devices with high reproducibility. Due to high purity and high yield, chemical vapor deposition (CVD) is a popular and advantageous growth method that offers the potential to grow nanotubes at an exact location with control over their length, diameter, shape and orientation.
Hence for many electronic, nanoelectromechanical systems and interconnect applications the integration possibilities of carbon nanostructures into existing CMOS-based industrial manufacturing processes is expected to be a ground breaking technological development. However, there are many engineering and materials issues inherent to CMOS-compatible device fabrication processes that need to be addressed before such integration can take place. Solutions to these issues have so far been long-awaited.
For instance, there are difficulties in growing nanostructures. Although numerous techniques have been developed and demonstrated to produce carbon based nanostructures, all have drawbacks for mass production and integration into existing industry manufacturing processes. Prominent drawbacks are: (a) control over predictable morphology with either semiconducting or metallic properties; (b) precise localization of the individual structures as and when they are grown, and (c) predictable electrical properties at the interface between the grown nanostructures and the substrate. There is no known single solution to solve all the aforementioned drawbacks. The most prominent techniques for synthesizing carbon nanostructures include are discharge (see, e.g., Iijima, S., Nature, 354, 56, (1991); and Kratschmer, W.; Lamb, L. D.; Fostiropoulos, K.; Huffman, D. R., Nature, 347, 354, (1990)), laser vaporization (see, e.g., Kroto, H. W.; Heath, J. R.; O'Brien, S. C.; Curl, R. F.; Smalley, R. E. Nature, 318, 162, (1985)), catalytic chemical-vapor deposition (CCVD), also referred to as CVD, (Cassell, A. M.; Raymakers, J. A.; Jing, K.; Hongjie, D., J. Phys. Chem. B, 103, (31), (1999)), and catalytic plasma enhanced chemical-vapor deposition (C-PECVD) (Cassell, A. M.; Qi, Y.; Cruden, B. A.; Jun, L.; Sarrazin, P. C.; Hou Tee, N.; Jie, H.; Meyyappan, M., Nanotechnology, 15(1), 9, (2004); and Meyyappan, M.; Delzeit, L.; Cassell, A.; Hash, D., Plasma Sources, Science and Technology, 12(2), 205, (2003)), all of which references are incorporated herein by reference in their entirety. Due to high purity and high yield, chemical vapor deposition (CVD) is a popular and advantageous growth method, and indeed, among all of the known growth techniques, CMOS compatibility has been demonstrated only for the CCVD method. (See, Tseng, et al. (Tseng, Y.-C.; Xuan, P.; Javey, A.; Malloy, R.; Wang, Q.; Bokor, J.; Dai, H., Nano Lett., 4(1), 123-127, (2004), incorporated herein by reference) where a monolithic integration of nanotube devices was performed on n-channel semiconductor (NMOS) circuitry.)
There are specific problems related to control of the properties of materials grown by the various methods, however. Even though numerous different growth methods exist for growing carbon nanostructures, controlling the interface properties between the nanostructures and the substrates, the body of the nanostructures, and the tip of the nanostructures have not yet been demonstrated to be well controlled by utilizing a single method of growth.
CVD typically employs a metal catalyst to facilitate carbon nanostructure growth. The main roles of the catalyst are to break bonds in the carbon carrying species, to absorb carbon at its surface, and to reform graphitic planes by diffusion of carbon through or around an interface (see, e.g., Kim, M. S.; Rodriguez, N. M.; Baker, R. T. K., Journal of Catalysis, 131, (1), 60, (1991); and Melechko, A. V.; Merkulov, V. I.; McKnight, T. E.; Guillorn, M. A.; Klein, K. L.; Lowndes, D. H.; Simpson, M. L., J. App. Phys., 97(4), 41301, (2005), both of which are incorporated herein by reference).
The growth of nanotubes is usually carried out on silicon or other semiconducting substrates. Growth from metal catalysts on CMOS-compatible conducting metal substrates or metal underlayers is almost lacking in the art and has proved to be far from trivial, at least because different metals require different conditions. This is because it has been found that it is hard to make a good contact between a growing nanostructure and a conducting substrate and produce good quality grown nanostructures. It has also proven difficult to control the diameter, length and morphology of the resulting nanostructures and with predictable interface properties between the nanostructures and the substrate. Nevertheless, for making CMOS-compatible structures, it is necessary to use a conducting substrate. In particular, this is because a metal substrate, or base layer, acts as bottom electrode for electrical connection to the nanostructures.
A method for producing arrays of carbon nanotubes on a metal underlayer, with a silicon buffer layer between the metal underlayer and a catalyst layer, is described in U.S. Patent Application Publication No. 2004/0101468 by Liu, et al. According to Liu et al., the buffer layer prevents catalyst from diffusing into the substrate and also prevents the metal underlayer from reacting with carbon source gas to, undesirably, form amorphous carbon instead of carbon nanostructures. In Liu, the process involves, inconveniently, annealing the substrate in air for 10 hours at 300-400° C. to form catalyst particles via oxidation of the catalyst layer, prior to forming the nanostructures. Each catalyst particle acts as a seed to promote growth of a nanostructure. The method of Liu, however, does not permit control of the composition or properties of the nanostructures, and the nanotubes produced are curved and disorganized.
Accordingly, there is a need for a method of growing carbon nanostructures on a metal substrate in such a way that various properties of the nanostructures can be controlled and so that interconnects and heat dissipators based on carbon nanostructures can be reliably fabricated.
The discussion of the background to the invention herein is included to explain the context of the invention. This is not to be taken as an admission that any of the material referred to was published, known, or part of the common general knowledge as at the priority date of any of the claims.
Throughout the description and claims of the specification the word “comprise” and variations thereof, such as “comprising” and “comprises”, is not intended to exclude other additives, components, integers or steps.